1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory (DRAM) device.
2. Description of the Related Art
Currently, memory cells each comprising one-transistor and one-capacitor of a DRAM device are further integrated to produce 4 megabit (M) DRAM's and samples of 16M DRAMs.
As the integration degree of the DRAMs is increased, however, the power consumption is greatly increased, and therefore, it is necessary to solve problems that arise due to this large power consumption. For example, a high heat radiation due to the large power consumption exceeds the capacity therefor of a conventional standard package, and thus this heat radiation must be reduced by improving circuit designs by reducing the size of memory cells, and by lowering a parasitic capacitance of a bit line, or the like. Furthermore, the high integration density of DRAM's allows a miniaturization of the memory cells and the DRAM device, which leads to a lowering of the capacitance of a charge storage capacitor, and this lowering of the capacitance leads to an increase of soft errors caused by an incidence of .alpha.-rays. Therefore, preferably the size of the charge storage capacitor is reduced without lowering the capacitance thereof.
Various improved DRAM devices are available; for example, in addition to an open bit line system, a folded bit line system by which the S/N (signal-to-noise ratio) is improved has been proposed, and with regard to the charge storage capacitor of a memory cell, in addition to a usual three dimensional stacked capacitor comprising a lower polycrystalline silicon (poly Si) electrode layer, an upper poly Si electrode layer, and a dielectric film sandwiched between the electrode layers, a tree-like multilayer stacked capacitor having a very high capacitance has been proposed.
Each of the memory cells of a DRAM device comprises a transfer transistor (MOS FET) T and a charge storage capacitor C arranged in a circuit as shown in FIG. 1. This circuit is used in both the open bit line system DRAM and the folded bit line system DRAM. The transistor T comprises a gate electrode 4 (i.e., a word line WL1), a source region 5 of a bit line contact region, and a drain region b of a storage electrode contact region, and the charge storage capacitor C comprises a storage electrode 8, a dielectric film (thin layer) 9, and an opposite electrode 10.
The open bit line system DRAM with a usual three-dimensional stacked capacitor has an arrangement (layout) as shown in FIG. 2. In FIG. 2, the same elements as shown in FIG. 1 are denoted by the same reference numerals and symbols. In this case, the word lines WL1 (4) and WL2 are made of poly Si, and the source region 5 and the drain region 6 are n.sup.+ -type impurity-doped regions. Reference numerals "7A" and "7B" indicate a bit line contact window and a storage electrode contact window, respectively, and are formed in an insulating layer. The storage electrode 8 of the capacitor C is made of poly Si and extends above the word line WL1 (4). The opposite electrode 10 is also made of poly Si and the bit line BL (12) is made of a conductor such as aluminum and metal silicide (e.g., WSi.sub.2). FIG. 2 has two additional scales at a right hand side and a lower side thereof, in which "a", "b" and "c" indicate a minimum line width, a first alignment tolerance, and a second alignment tolerance, and are used for a comparison of the memory cell size (area) as explained hereafter in detail.
The open bit line system DRAM device has been replaced by a folded bit line system DRAM device developed to increase the S/N.
The folded bit line system DRAM device with a usual three-dimensional stacked capacitor is shown in FIG. 3 and 4; (for example, cf. Takemae et al, "Development of 1M DRAM for Aiming at Easy Operation and Production", Nikkei Electronics, No. 370, Jun. 3, 1985, PP. 209-231). FIG. 3 shows a layout (a schematic partial plan view) of the DRAM device and FIG. 4 shows a schematic sectional partial view of the device taken along the line IV--IV of FIG. 3. Note, in these drawings, the same or corresponding elements as those shown in the previous figures are denoted by the same reference numerals and symbols.
The DRAM device is produced by using a p-type silicon substrate (wafer) 1, and is provided with a field insulating film 2 of silicon dioxide (SiO.sub.2) a gate insulating film 3 of SiO.sub.2 , an insulating interlayer (film) 7 of SiO.sub.2 , and an insulating interlayer (film) 11 of phosphosilicate glass (PSG). The stacked capacitor consists of the storage (lower) electrode 8 of poly Si, the dielectric film 9 of SiO.sub.2, and the opposite (upper) electrode 10 of poly Si. Since the storage electrode 8 extends above the word lines WL1 and WL2, the capacitance of the capacitor is increased, and as an electric charge stored in the capacitor of a memory cell corresponds to memory information, as the capacitance of the capacitor is increased, the S/N is improved.
Nevertheless, the miniaturization of DRAMs means that the size of the charge storage capacitor is reduced, and thus there is a possibility of a shortage of the capacitance. Accordingly, a tree-like multilayer stacked capacitor, in which the capacitance (electric charge storing ability) is greatly increased, has been proposed (for example, U.S. Ser. No. 07/206,791 filed on Jun. 15, 1988, now abandoned, and Japanese Patent Application Nos. 62-149143, 62-30641 and 62-314764).
FIG. 5 shows a schematic sectional view of the DRAM device with the tree-like multilayer stacked capacitor, in which drawing the same or corresponding elements as those shown in the previous figures are denoted by the same reference numerals and symbols. As can be seen from FIG. 5, the capacitor consisting of the storage electrode 8, the dielectric film 9 and the opposite electrode 11 has three fin portions 15, 17, and 19, and thus the capacitance thereof is much larger than that of the capacitor of FIG. 4, and as long as such a tree-like stacked capacitor structure is adopted in DRAM devices, the capacitance thereof will allow a further miniaturization of DRAMs, to produce, for example, 16M DRAMs.
Nevertheless, this increase of capacitance due to the tree-like structure causes problems in the production process. Namely, the height of the charge storage capacitance is increased to make a distance between the substrate surface and the top surface of the insulating film 11 greater, which results in a poor step coverage of the bit line 12, regardless of FIG. 5.
The problem (i.e., poor step coverage) had been solved by an improved DRAM device shown in FIGS. 6 and 7, in which the bit line 12 is formed prior to the formation of the tree-like capacitor. FIG. 6 shows a schematic sectional partial view of the improved DRAM device and FIG. 7 shows a layout (a schematic partial plan view) of the device, in which drawings the same or corresponding elements as those shown in the previous figures are denoted by the same reference numerals and symbols. In FIG. 6, the bit line 12 has a doublelayer structure of a poly Si film and a WSi.sub.2 film, and an additional insulating interlayer 13 of silicon nitride (Si.sub.3 N.sub.4) is formed to cover the bit line 12 and the insulating interlayer 7. The tree-like stacked capacitor of the improved DRAM device is the same as that shown in FIG. 5, except for the shape of the opposite electrode 10. FIG. 7 has additional scales similar to those of FIG. 2 at the right hand side and lower side thereof, and these are used for a comparison of the memory cell size (area). When the bit line 12 is formed, since a large step (tree-like structure) does not exist, the step coverage problem is avoided. Furthermore, the fin portions 15, 17 and 19 of the capacitor (FIG. 6) can be further extended above the bit line 12 and beyond the word line WL1 (gate electrode 4), so that the capacitance is further increased.
Where the technique of the improved DRAM device of FIGS. 6 and 7 is applied to an open bit line system DRAM device, a layout (arrangement) of the latter device is obtained as shown in FIG. 8. This layout was formed by the present inventor during experiments in the making of the present invention. In FIG. 8, the same elements as those shown in FIGS. 6 and 7 are denoted by the same reference numerals and symbols, and an additional two scales similar to those of FIGS. 2 and 7 are also shown in FIG. 8.
Although the folded bit line system having an improved S/N is superior to the open bit line system, the tree-like multilayer stacked capacitor provides a capacitance sufficient to obtain a good S/N, in spite of miniaturization, with the result that the open bit line system is preferable since the bit line (parasitic) capacitance is lower than that of the folded bit line system, whereby an output signal voltage is increased and the power consumption is reduced.
The parasitic capacitance of the bit line will be explained.
When the word line WL1 (4) is ON, the following formula is obtained: EQU C.sub.BL V.sub.0 +C.sub.cell V.sub.1 =(C.sub.BL +C.sub.cell)V
where, C.sub.cell is the capacitance of the charge storage capacitor described with reference to FIGS. 1 to 8, C.sub.BL is the parasitic capacitance of the bit line BL (12), V.sub.0 is an initial bit line voltage, V.sub.1 is a voltage of the capacitor, and V is a voltage of the word line WL 1 in an ON condition.
The output signal voltage .DELTA.V is as follows: ##EQU1## and thus is largely dependent upon a ratio of the bit line capacitance C.sub.BL to the capacitor's capacitance C.sub.cell. Therefore, preferably the bit line capacitance is made as low as possible.
In the operation of the DRAM device, to prevent a loss of information, a refresh, i.e., reading and rewriting, operation is periodically carried out at predetermined intervals. When rewriting, the charge storage capacitor must be made high ("H") level by charging up the bit line to the supply (source) voltage. This charge up electric current accounts for about half of the total power consumption. The charge up and discharge electric current is proportional to the bit line capacitance, and thus preferably the bit line capacitance is lowered.
The simplest and most certain means of lowering the bit line parasitic capacitance is to shorten the bit line length.
The bit line length of the folded bit line system DRAM device of FIGS. 6 and 7 is explained with reference to FIG. 9. FIG. 9 schematically shows a relationship between bit lines BL1A, BL1B, BL2A, BL2B, memory cells MC, and sense amplifiers SA1, SA2. In this case, a pair of memory cells MC constitute a unit cell. The length of each of the bit lines BL1A . . . is relatively long, and thus the bit line parasitic capacitance is high. For example, where a sense amplifier SA is provided with 512 memory cells, although 256 cells per bit line exist, there are 512 word lines per bit line. Namely, 512 word lines cross a bit line, and thus the bit line length corresponds to at least the total pitch of 512 word lines.
Further, in addition to the high bit line parasitic capacitance in the above-mentioned folded bit line system DRAM devices, these devices and the open bit system DRAM device of FIG. 8 have a problem of memory cell size (area).
Prior to a discussion of the cell sizes of the DRAM devices of FIGS. 7, 2 and 8, the first and second alignment tolerances "b" and "c" shown in the additional scales of the drawings are explained with reference to FIGS. 10A, 10B, 11A and 11B. In the drawings, reference numerals 31, 32, 33, 34 and 35 indicate a silicon substrate, an insulating film of SiO.sub.2, a poly Si electrode, another (e.g., gate) insulating film, and another (e.g., gate) electrode of poly Si, respectively.
FIGS. 10A and 10B explain the formation of the first alignment tolerance "b". The size of the poly Si electrode 33 must be larger than a contact window size by at least the alignment tolerance "b", as shown in FIG. 10A. If the poly Si electrode 33 is patterned to form a space between the electrode 33 and the insulating film 32, as shown in FIG. 10B, a portion of the silicon substrate 31 is etched at the patterning step.
FIGS. 11A and 11B explain the formation of the second alignment tolerance "c". To bring the poly Si electrode 33 into appropriate contact with the silicon substrate 31, the insulating film 32 must be selectively etched to provide the alignment tolerance "c" between a contact window and the gate electrode 35, as shown in FIG. 11A. If the selective etching of the insulating film is not appropriate, as shown in FIG. 11B, a short occurs between the poly Si electrode 33 and the (gate) electrode 35.
Therefore, the following relationship is determined between the minimum line width "a", and the alignment tolerances "b" and "c": EQU a&gt;c&gt;b
In general the conditions "a=4b" and "c=2b" are predetermined.
Taking the above-mentioned explanation and conditions into consideration, the memory cell size of the DRAM device of FIG. 7 is calculated as follows: ##EQU2## This cell size is relatively large, and if the memory cell size can be further reduced without affecting the properties and functions of the DRAM device, good results will be obtained together with an even better integration.
The memory cell size of the DRAM device of FIG. 2 is calculated as follows: ##EQU3##
The memory cell size of the DRAM device of FIG. 8 is calculated as follows: ##EQU4##